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Whenever the I C module is waiting for interaction from software, it holds the bus clock SCL low, freezing
depends on the current state the of the I C module. This state can be read from the I2Cn_STATE register.
As an example, Table 15.4 (p. 154) shows the different states the I C goes through when operating
which can be used to identify exactly what the I C module is waiting for.
The different interactions used by the I C module are listed in Table 15.3 (p. 152) in prioritized order. If
Table 15.3. I C Interactions in Prioritized Order
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15.3.7.2 Interactions
2
all bus activities, and the BUSHOLD interrupt flag in I2Cn_IF is set. The action(s) required by software
2
2
as a Master Transmitter, i.e. a master that transmits data to a slave. As seen in the table, when a start
condition has been transmitted, a requirement is that there is an address and an R/W bit in the transmit
buffer. If the transmit buffer is empty, then the BUSHOLD interrupt flag is set, and the bus is held until
data becomes available in the buffer. While waiting for the address, I2Cn_STATE has a value 0x57,
2
Note
The bus would never stop at state 0x57 if the address was available in the transmit buffer.
2
a set of different courses of action are possible from a given state, the course of action using the highest
priority interactions, that first has everything it is waiting for is the one that is taken.
2
Interaction
STOP*
Priority
1
Software action
Set the STOP command bit
in I2Cn_CMD
Automatically continues if
PSTOP is set (STOP
pending) in I2Cn_STATUS
ABORT
2
Set the ABORT command bit Never, the transmission is
in I2Cn_CMD
aborted
CONT*
3
Set the CONT command bit
in I2Cn_CMD
PCONT is set in
I2Cn_STATUS (CONT
pending)
NACK*
4
Set the NACK command bit
in I2Cn_CMD
PNACK is set in
I2Cn_STATUS (NACK
pending)
ACK*
5
Set the ACK command bit in
I2Cn_CMD
AUTOACK is set in
I2Cn_CTRL or PACK is
set in I2Cn_STATUS (ACK
pending)
ADDR+W -> TXDATA
ADDR+R -> TXDATA
START*
6
7
8
Write an address to the
transmit buffer with the R/W
bit set
Write an address to the
transmit buffer with the R/W
bit cleared
Set the START command bit
in I2Cn_CMD
Address is available in
transmit buffer with R/W bit
set
Address is available in
transmit buffer with R/W bit
cleared
PSTART is set in
I2Cn_STATUS (START
pending)
TXDATA
RXDATA
None
9
10
11
Write data to the transmit
buffer
Read data from receive
buffer
No interaction is required
Data is available in transmit
buffer
Space is available in receive
buffer
When such a command is issued before it can be used/consumed by the I C module, the command is
The commands marked with a * in Table 15.3 (p. 152) can be issued before an interaction is required.
2
2011-04-12 - d0001_Rev1.10
152
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